In a semiconductor memory circuit each of the memory cells is accessed by applying a high voltage to a row line that drives an access transistor for the addressed memory cell. The row line is activated by a decoder circuit which is driven in response to a multi-bit memory address signal. The row line selected by the address is driven to a high level by the decoder circuit. Heretofore, it has been a frequent practice to permit the row lines to float at times when another row line is selected by the decoder. But in memory circuits in which multiple bit lines can go high during an active cycle, the capacitive coupling between these bit lines and the floating row lines causes these floating row lines to be capacitively charged positive. This positive voltage can turn on the access transistors for the memory cells connected to the floating row lines. This inadvert activation of memory cells can destroy the data state stored therein. Thus, when these memory cells are later accessed, erroneous data can be read out.
In view of this problem, there exists a need for a circuit which holds nonselected row lines at a low voltage state to reduce the effect of capacitive coupling but also permits a selected row line to be charged without drawing a substantial amount of current from the row driver transistor. Further this circuit must have a topological configuration adaptable for integration in a very dense integrated memory circuit.